Merge branch 'pm-cpu'

* pm-cpu:
  x86: remove duplicate turbo ratio limit MSRs
  tools/power turbostat: Replace MSR_NHM_TURBO_RATIO_LIMIT
  cpufreq: intel_pstate: Replace MSR_NHM_TURBO_RATIO_LIMIT

diff --combined drivers/cpufreq/intel_pstate.c
index d8028de,facf05c..9ec033b
--- 1/drivers/cpufreq/intel_pstate.c
--- 2/drivers/cpufreq/intel_pstate.c
+++ b/drivers/cpufreq/intel_pstate.c
@@@ -97,6 -97,7 +97,6 @@@ static inline u64 div_ext_fp(u64 x, u6
   *                    read from MPERF MSR between last and current sample
   * @tsc:              Difference of time stamp counter between last and
   *                    current sample
 - * @freq:             Effective frequency calculated from APERF/MPERF
   * @time:             Current time from scheduler
   *
   * This structure is used in the cpudata structure to store performance sample
@@@ -108,6 -109,7 +108,6 @@@ struct sample 
        u64 aperf;
        u64 mperf;
        u64 tsc;
 -      int freq;
        u64 time;
  };
  
@@@ -806,8 -808,7 +806,8 @@@ static void __init intel_pstate_sysfs_e
  static void intel_pstate_hwp_enable(struct cpudata *cpudata)
  {
        /* First disable HWP notification interrupt as we don't process them */
 -      wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
 +      if (static_cpu_has(X86_FEATURE_HWP_NOTIFY))
 +              wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
  
        wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
  }
@@@ -944,7 -945,7 +944,7 @@@ static int core_get_max_pstate(void
                        if (err)
                                goto skip_tar;
  
 -                      tdp_msr = MSR_CONFIG_TDP_NOMINAL + tdp_ctrl;
 +                      tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x3);
                        err = rdmsrl_safe(tdp_msr, &tdp_ratio);
                        if (err)
                                goto skip_tar;
@@@ -972,7 -973,7 +972,7 @@@ static int core_get_turbo_pstate(void
        u64 value;
        int nont, ret;
  
-       rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value);
+       rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
        nont = core_get_max_pstate();
        ret = (value) & 255;
        if (ret <= nont)
@@@ -1001,7 -1002,7 +1001,7 @@@ static int knl_get_turbo_pstate(void
        u64 value;
        int nont, ret;
  
-       rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value);
+       rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
        nont = core_get_max_pstate();
        ret = (((value) >> 8) & 0xFF);
        if (ret <= nont)
@@@ -1133,12 -1134,17 +1133,12 @@@ static void intel_pstate_get_min_max(st
        *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf);
  }
  
 -static inline void intel_pstate_record_pstate(struct cpudata *cpu, int pstate)
 -{
 -      trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
 -      cpu->pstate.current_pstate = pstate;
 -}
 -
  static void intel_pstate_set_min_pstate(struct cpudata *cpu)
  {
        int pstate = cpu->pstate.min_pstate;
  
 -      intel_pstate_record_pstate(cpu, pstate);
 +      trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
 +      cpu->pstate.current_pstate = pstate;
        /*
         * Generally, there is no guarantee that this code will always run on
         * the CPU being updated, so force the register update to run on the
@@@ -1298,11 -1304,10 +1298,11 @@@ static inline void intel_pstate_update_
  
        intel_pstate_get_min_max(cpu, &min_perf, &max_perf);
        pstate = clamp_t(int, pstate, min_perf, max_perf);
 +      trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
        if (pstate == cpu->pstate.current_pstate)
                return;
  
 -      intel_pstate_record_pstate(cpu, pstate);
 +      cpu->pstate.current_pstate = pstate;
        wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
  }