CHROMIUM: gpio: nm10_gpio: Add device ID of Intel HM65 chipset
authorSameer Nanda <snanda@chromium.org>
Mon, 18 Jul 2011 21:53:09 +0000 (14:53 -0700)
committerGrant Grundler <grundler@google.com>
Thu, 24 May 2012 22:14:35 +0000 (15:14 -0700)
The GPIO access mechanism on the HM65 PCH is the same a NM10. Simply
adding the device ID of HM65 to this driver instead of writing a new
driver that essentially does the same thing.

BUG=chrome-os-partner:4977
TEST=crossystem should report the correct values of recoverysw_cur and
devsw_cur with this driver in place,

Change-Id: I5bb0082b77dc4dec8739f9e24d92be485e3f28ae
Signed-off-by: Sameer Nanda <snanda@chromium.org>
Reviewed-on: http://gerrit.chromium.org/gerrit/4272
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Olof Johansson <olofj@chromium.org>
drivers/gpio/nm10_gpio.c
include/linux/pci_ids.h

index 492c559..f5f74b1 100644 (file)
@@ -341,6 +341,8 @@ static void nm10_gpio_remove(struct pci_dev *pdev)
 
 static struct pci_device_id nm10_gpio_ids[] = {
        {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC)},
+       {PCI_DEVICE(PCI_VENDOR_ID_INTEL,
+               PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_HM65)},
        {0,}
 };
 
index 3329965..0ecacad 100644 (file)
 #define PCI_DEVICE_ID_INTEL_82845_HB   0x1a30
 #define PCI_DEVICE_ID_INTEL_IOAT       0x1a38
 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN        0x1c41
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_HM65       0x1c49
 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX        0x1c5f
 #define PCI_DEVICE_ID_INTEL_PATSBURG_LPC_0     0x1d40
 #define PCI_DEVICE_ID_INTEL_PATSBURG_LPC_1     0x1d41