V4L2_MBUS_FMT_BGR565_2X8_LE = 0x1006,
V4L2_MBUS_FMT_RGB565_2X8_BE = 0x1007,
V4L2_MBUS_FMT_RGB565_2X8_LE = 0x1008,
+ V4L2_MBUS_FMT_XRGB8888_4X8_LE = 0x1009,
/* YUV (including grey) - next is 0x2014 */
V4L2_MBUS_FMT_Y8_1X8 = 0x2001,
V4L2_MBUS_FMT_VYUY8_1X16 = 0x2010,
V4L2_MBUS_FMT_YUYV8_1X16 = 0x2011,
V4L2_MBUS_FMT_YVYU8_1X16 = 0x2012,
+ V4L2_MBUS_FMT_YUV8_1X24 = 0x2014,
V4L2_MBUS_FMT_YUYV10_1X20 = 0x200d,
V4L2_MBUS_FMT_YVYU10_1X20 = 0x200e,
#define V4L2_DV_1080P50 17 /* BT.1120 */
#define V4L2_DV_1080P60 18 /* BT.1120 */
+#define V4L2_DV_480P60 19
+#define V4L2_DV_1080I59_94 20
+#define V4L2_DV_1080P59_94 21
+
+#define V4L2_DV_720P60_FP 22
+#define V4L2_DV_720P60_SB_HALF 23
+#define V4L2_DV_720P60_TB 24
+#define V4L2_DV_720P59_94_FP 25
+#define V4L2_DV_720P59_94_SB_HALF 26
+#define V4L2_DV_720P59_94_TB 27
+#define V4L2_DV_720P50_FP 28
+#define V4L2_DV_720P50_SB_HALF 29
+#define V4L2_DV_720P50_TB 30
+#define V4L2_DV_1080P24_FP 31
+#define V4L2_DV_1080P24_SB_HALF 32
+#define V4L2_DV_1080P24_TB 33
+#define V4L2_DV_1080P23_98_FP 34
+#define V4L2_DV_1080P23_98_SB_HALF 35
+#define V4L2_DV_1080P23_98_TB 36
+#define V4L2_DV_1080I60_SB_HALF 37
+#define V4L2_DV_1080I59_94_SB_HALF 38
+#define V4L2_DV_1080I50_SB_HALF 39
+#define V4L2_DV_1080P60_SB_HALF 40
+#define V4L2_DV_1080P60_TB 41
+#define V4L2_DV_1080P30_FP 42
+#define V4L2_DV_1080P30_SB_HALF 43
+#define V4L2_DV_1080P30_TB 44
/*
* D V B T T I M I N G S
*/
#define V4L2_CTRL_CLASS_FM_TX 0x009b0000 /* FM Modulator control class */
#define V4L2_CTRL_CLASS_FLASH 0x009c0000 /* Camera flash controls */
#define V4L2_CTRL_CLASS_JPEG 0x009d0000 /* JPEG-compression controls */
+#define V4L2_CID_EXYNOS_BASE (V4L2_CTRL_CLASS_USER | 0x2000)
+#define V4L2_CID_TV_HPD_STATUS (V4L2_CID_EXYNOS_BASE + 55)
#define V4L2_CTRL_ID_MASK (0x0fffffff)
#define V4L2_CTRL_ID2CLASS(id) ((id) & 0x0fff0000UL)