CHROMIUM: arm: exynos: s5p-mfc: Disable PMU configuration for MFC

For s5p-mfc, initializing the PMU configuration for the MFC block
appears to occasionally cause the MFC block to run in a
lower-performance state during video decoding, resulting in sub-realtime
performance for 1080p video decoding.  Revert the PMU configuration,
just for the MFC block, while further debugging occurs.

BUG=chromium:220275
TEST=local build, run on snow

Change-Id: I70b04de1cd872a9b87b6e8cf8e7e85e48c87ad87
Reviewed-on: https://gerrit.chromium.org/gerrit/45928
Tested-by: John Sheu <sheu@chromium.org>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Commit-Queue: John Sheu <sheu@chromium.org>

diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index eb36bbc..f24370a 100644 (file)
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -291,21 +291,21 @@ static struct exynos4_pmu_conf exynos5250_pmu_config[] = {
        { EXYNOS5_GPS_SYS_PWR_REG,                      { 0x7, 0x0, 0x0} },
        { EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG,         { 0x0, 0x0, 0x0} },
        { EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG,          { 0x0, 0x0, 0x0} },
-       { EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG,          { 0x0, 0x0, 0x0} },
+       { EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
        { EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG,          { 0x0, 0x0, 0x0} },
        { EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG,        { 0x0, 0x0, 0x0} },
        { EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG,          { 0x0, 0x0, 0x0} },
        { EXYNOS5_CMU_CLKSTOP_GPS_SYS_PWR_REG,          { 0x0, 0x0, 0x0} },
        { EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG,          { 0x0, 0x0, 0x0} },
        { EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG,           { 0x0, 0x0, 0x0} },
-       { EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG,           { 0x0, 0x0, 0x0} },
+       { EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG,           { 0x1, 0x0, 0x0} },
        { EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG,           { 0x0, 0x0, 0x0} },
        { EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG,         { 0x0, 0x0, 0x0} },
        { EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG,           { 0x0, 0x0, 0x0} },
        { EXYNOS5_CMU_SYSCLK_GPS_SYS_PWR_REG,           { 0x0, 0x0, 0x0} },
        { EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG,           { 0x0, 0x0, 0x0} },
        /* CMU_RESET_ISP_SYS_PWR_REG handled in exynos5250_disable_isp() */
-       { EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG,            { 0x0, 0x0, 0x0} },
+       { EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG,            { 0x1, 0x0, 0x0} },
        { EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG,            { 0x0, 0x0, 0x0} },
        { EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG,          { 0x0, 0x0, 0x0} },
        { EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG,            { 0x0, 0x0, 0x0} },
@@ -346,18 +346,15 @@ void __iomem *exynos5_list_diable_wfi_wfe[] = {
 void __iomem *exynos5_list_disable_pmu_reg[] = {
        EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG,
        EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG,
-       EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG,
        EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG,
        EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG,
        EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG,
        EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG,
        EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG,
-       EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG,
        EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG,
        EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG,
        EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG,
        EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG,
-       EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG,
        EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG,
        EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG,
        EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG,