CHROMIUM: nm10_gpio: support additional LPC IDs

Adding more LPC device IDs of the Intel 6 Series and C200 Series
chipsets.

This has been tested and works on HM65 and HM67 variants.

BUG=none
TEST=run crossystem and ensure that the current values of recovery and
dev switches are correct

Change-Id: I895fca9bd5c23caeb2b4a3b06bbb20bc46d8691a
Signed-off-by: Sameer Nanda <snanda@chromium.org>
Reviewed-on: http://gerrit.chromium.org/gerrit/5682
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>

diff --git a/drivers/gpio/nm10_gpio.c b/drivers/gpio/nm10_gpio.c
index f5f74b1..2885dd8 100644 (file)
--- a/drivers/gpio/nm10_gpio.c
+++ b/drivers/gpio/nm10_gpio.c
@@ -341,8 +341,36 @@ static void nm10_gpio_remove(struct pci_dev *pdev)
 
 static struct pci_device_id nm10_gpio_ids[] = {
        {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC)},
+       {PCI_DEVICE(PCI_VENDOR_ID_INTEL,
+               PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_Z68)},
+       {PCI_DEVICE(PCI_VENDOR_ID_INTEL,
+               PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_P67)},
+       {PCI_DEVICE(PCI_VENDOR_ID_INTEL,
+               PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_UM67)},
        {PCI_DEVICE(PCI_VENDOR_ID_INTEL,
                PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_HM65)},
+       {PCI_DEVICE(PCI_VENDOR_ID_INTEL,
+               PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_H67)},
+       {PCI_DEVICE(PCI_VENDOR_ID_INTEL,
+               PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_HM67)},
+       {PCI_DEVICE(PCI_VENDOR_ID_INTEL,
+               PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_Q65)},
+       {PCI_DEVICE(PCI_VENDOR_ID_INTEL,
+               PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_QS67)},
+       {PCI_DEVICE(PCI_VENDOR_ID_INTEL,
+               PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_Q67)},
+       {PCI_DEVICE(PCI_VENDOR_ID_INTEL,
+               PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_QM67)},
+       {PCI_DEVICE(PCI_VENDOR_ID_INTEL,
+               PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_B65)},
+       {PCI_DEVICE(PCI_VENDOR_ID_INTEL,
+               PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_C202)},
+       {PCI_DEVICE(PCI_VENDOR_ID_INTEL,
+               PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_C204)},
+       {PCI_DEVICE(PCI_VENDOR_ID_INTEL,
+               PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_C206)},
+       {PCI_DEVICE(PCI_VENDOR_ID_INTEL,
+               PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_H61)},
        {0,}
 };
 

diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 0ecacad..16fb10d 100644 (file)
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2526,7 +2526,21 @@
 #define PCI_DEVICE_ID_INTEL_82845_HB   0x1a30
 #define PCI_DEVICE_ID_INTEL_IOAT       0x1a38
 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN        0x1c41
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_Z68                0x1c44
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_P67                0x1c46
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_UM67       0x1c47
 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_HM65       0x1c49
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_H67                0x1c4a
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_HM67       0x1c4b
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_Q65                0x1c4c
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_QS67       0x1c4d
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_Q67                0x1c4e
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_QM67       0x1c4f
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_B65                0x1c50
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_C202       0x1c52
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_C204       0x1c54
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_C206       0x1c56
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_H61                0x1c5c
 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX        0x1c5f
 #define PCI_DEVICE_ID_INTEL_PATSBURG_LPC_0     0x1d40
 #define PCI_DEVICE_ID_INTEL_PATSBURG_LPC_1     0x1d41